FIELD OF THE INVENTION
The invention relates to a DRAM cell configuration and a method for its production.
In DRAM cell configurations, that is to say memory cell configurations with dynamic random access, use is made almost exclusively of so-called single-transistor memory cells. A single-transistor memory cell includes a read-out transistor and a storage capacitor. The information is stored in the storage capacitor in the form of an electric charge, which represents a logic value, 0 or 1. That information can be read out through a bit line by driving a readout transistor over a word line.
Since storage density increases from memory generation to memory generation, the required area of the single-transistor memory cell must be reduced from generation to generation. Since limits are imposed on the reduction of the structure sizes by a minimum structure size F which can be produced by using the respective technology, that is also associated with an alteration of the single-transistor memory cell. Thus, up until the 1 Mbit generation, both the read-out transistor and the storage capacitor were realized as planar components. Starting with the 4 Mbit memory generation, a further reduction in area had to be effected through the use of a three-dimensional configuration of the read-out transistor and the storage capacitor.
One possibility is to realize the storage capacitor in a trench rather than in a planar manner (see, for example, a paper by K. Yamada et al. entitled "A Deep Trenched Capacitor Technology for 4 Mbit DRAMs", in Proc. Intern. Electronic Devices and Materials IEDM 85, page 702).
Another possibility is to use vertical MOS transistors as described in U.S. Pat. No. 5,376,575, for example. In the production method described therein, each vertical MOS transistor encompasses two opposite sides of a trench along which a bit line runs. Doped regions which act as a drain region of the MOS transistors are provided in the upper area of the sides. The surface of the sides is provided with gate oxide. A gate electrode is provided which covers the opposite surface of the gate oxide. The gate electrode is insulated from an inferior, buried bit line and from a superior storage node, in each case by an insulating layer. Shallow trenches which run transversely to the bit lines and in which word lines running transversely to the bit lines are disposed are provided in the surface of the substrate. The word lines laterally adjoin the gate electrode and are thus connected thereto. The smallest memory cell area that can be achieved using that method is 6 F.sup.2.
German Published, Non-Prosecuted Patent Application DE 38 44 120 A1 discloses a DRAM configuration in which trenches are provided in a semiconductor substrate. A drain region is provided at the bottom of the trench. A source region is provided at the surface of the substrate. The side walls of the trench are provided with gate oxide and a gate electrode and act as a channel region. The gate electrodes are embedded in an insulation layer in which a contact hole reaches down to the surface of the drain region located at the bottom of the trench and is provided with an electrode. A capacitor is provided laterally with respect to the trench on the surface of the semiconductor substrate. The lateral configuration of the capacitor and the transistor results in an increased area requirement of the memory cell.
A DRAM cell configuration in which read-out transistors are constructed as vertical transistors is mentioned in a paper by P. Chatterjee et al. in IEDM 86 pages 128-131. A read-out transistor has a first source/drain region which annularly-forms a ring surrounds a gate electrode and is part of a bit line. A second source/drain region of the read-out transistor is produced by outdiffusion of dopant of a storage node which is realized in a depression and is disposed underneath the gate electrode. Word lines, which are in part composed of gate electrodes, run above the bit lines. The read-out transistor encompasses at least sides of the gate electrode which are parallel to the bit lines. The area of a memory cell is 9 F.sup.2.
German Patent DE 195 19 160 C1 proposes a DRAM cell configuration which includes one vertical MOS transistor per memory cell. A first source/drain region of the transistor is connected to a storage node of a storage capacitor, a channel region of the transistor is annularly enclosed by a gate electrode, and a second source-drain region of the transistor is connected to a buried bit line. The storage capacitor is either a planar capacitor or a stacked capacitor. The DRAM cell configuration can be produced with a memory cell area of 4 F.sup.2.
The area of a memory cell of a DRAM in the 1 Gbit generation is intended to be only about 0.2 .mu.m.sup.2. In that case, the storage capacitor must have a capacitance of 20 to 30 fF. Such a capacitance can only be achieved at great expense given a cell area of the kind that is available in the 1 Gbit generation, both in the case of planar capacitors and in the case of stacked capacitors: in the case of planar capacitors, it is necessary to apply a capacitor dielectric made of a material having a particularly high dielectric constant. Since the known ferroelectric and paraelectric materials which are suitable therefor contaminate the apparatuses which are usually used to produce DRAMs, the DRAM to be produced must be placed into an additional second apparatus for the application of the dielectric. In the case of the stacked capacitor, a relatively complicated polysilicon structure is required in order to enlarge the area and thus the capacitance of the storage capacitor, which structure is all the more difficult to produce as the cell area becomes smaller.